1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory. It is particularly related to a nonvolatile semiconductor memory having characteristics for write-in methods.
2. Description of the Related Art
Conventionally, a NAND flash EEPROM is known as an electrically erasable and highly integrated nonvolatile semiconductor memory. A memory transistor for the NAND flash EEPROM has a structure in which charge accumulation layers or films and control gates are stacked with an inter lying insulating layer on a semiconductor substrate. A NAND cell unit is configured by connecting a plurality of memory cell transistors in series as columns in a shape such that neighboring memory cells share a common source or a drain region, and arranging select gate transistors at both sides thereof.
A memory cell array is configured with arranging NAND cell units in a matrix. In addition, NAND cell units arranged in rows are called a NAND cell block. Gates of select gate transistors arranged in the same row are connected to the same select gate line, and control gates of memory cell transistors arranged in the same row are connected to the same control gate line. When N memory cell transistors are connected in series in a NAND cell unit, N control gate lines are included in a single NAND cell block.
The nonvolatile memory cell transistor stores data defined by the charge accumulation state of a floating gate. Specifically, storage of binary data is performed with, for example, voltages resulting from injecting electrons into a floating gate through a channel which are higher than a certain threshold voltage as data “0” and lower voltages resulting from discharging the electrons stored in the floating gate through the same channel as data “1”. Recently, a multiple-valued storage method such as a 4-valued storage has also been implemented by more finely controlling the threshold distribution.
When performing data write-in, to begin with, the entire data stored in the NAND cell block is erased all at once. This is performed by setting all control gate lines (word lines) of the selected NAND cell block to a low voltage Vss (for example, 0V), applying a high positive voltage Vera (erasure voltage, for example, 20V) to a p-well containing the cell array, and discharging the floating gate electrodes to the channel. Accordingly, all the data in the NAND cell block becomes data “1”. Not only can a NAND cell block be erased all at once, but so can an entire chip.
Writing data is performed all at once after the collective data erasure described above for a plurality of memory cell transistors connected to the selected control gate lines. The write-in unit is normally defined as one page; however recently, there are instances where a plurality of pages is allotted to a single control gate line. The write-in order for the control gate lines in the NAND cell block may be an arbitrary order (random write-in), or an order in a certain single direction (sequential write-in). Sequential write-in is normally performed in an order from the control gate line on the source side.
Applying a high positive voltage Vpgm (a write-in voltage, for example, 20V) to the selected control gate line so as to write in a control gate line all at once allows execution of two types of simultaneous data write-in: in the case of data “0”, electrons are injected from the channel to the floating gate (namely, “0” write-in), and in the case of data “1”, electron injection is restricted (namely, write-restricted, or “1” write-in). Implementing such control gate line collective write-in requires controlling the channel voltage for the memory transistor depending on data. For example, in the case of data “0”, the channel voltage is kept low, and when a write-in voltage Vpgm is applied to the control gate, a corresponding large electric field is impressed on the gate insulating film below the floating gate. On the other hand, in the case of data “1”, electron injection to the floating gate is restricted by boosting the channel voltage and lowering the electric field to be impressed on the gate insulating film. At this time, if the boost in the channel voltage is insufficient, electron injection occurs and the threshold then fluctuates, even with a “1” write-in memory transistor. This phenomenon is hereafter called as, “an erroneous write-in”. Implementing the write-in operation for NAND flash EEPROM requires controlling the threshold fluctuation due to an erroneous write-in within the specification limits so that faulty operations do not occur.
As methods for channel voltage control during write-in, a self-boosting (SB) write-in method as described in K. D. Suh, et.al, “A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30. NO. 11, NOVEMBER 1995, p. 1149–1156, and a local self-boosting (LSB) method are known as disclosed in Japanese Laid-open Patent Application No. Hei 8-279297. In addition, an erasure area self-boosting (EASB) method has been proposed as disclosed in 8-279297. On the other hand, as a method for improving initial charging voltage, a channel voltage boosting method has been proposed, which increases the initial voltage by transferring a bit line voltage which does not go below the threshold through temporarily boosting the voltage of the bit line side select gate line during initial voltage transfer, as disclosed in Japanese Laid-open Patent Application No. Hei 10-223866.
As discussed above, the phenomenon where the threshold of a memory transistor, which needs to maintain an erased state, varies during the write-in operation in NAND flash EEPROM is called “erroneous write-in”. There are two types of stress that cause “erroneous write-in”: “Vpgm stress” and “Vpass stress”.
The write-in restriction (“1” write-in) for unselected memory cell transistors, which are connected to a selected control gate line and to which are applied a write-in voltage Vpgm, is performed by boosting the channel voltage for the unselected memory cell transistors through capacitive coupling of one to a plurality of unselected control gate lines. An intermediate voltage Vpass is applied to all or a part of the unselected control gate lines for boosting the channel voltage, however, an erroneous write-in occurs if the intermediate voltage Vpass is too small. This stress applied to the unselected memory cell transistors is called “Vpgm stress”.
On the other hand, since the channel voltage for the unselected memory cell transistors in the NAND cell unit to which “0” write-in is to be performed is small, erroneous write-in occurs if the aforementioned intermediate voltage Vpass is too large. When this type of stress is applied to the unselected memory cell transistors, it is called “Vpass stress”.
There are two types of write-in order for the control gate lines in the NAND cell block: a random write-in method for writing in an arbitrary order regardless of control gate line location, and a sequential write-in method for writing in an order from, for example, the source side control gate line. Recently, however, there is a tendency to use the latter sequential write-in method. In the case of the sequential write-in method, all of the selected memory cell transistors and the unselected memory cell transistors closer to the bit line side are in an erased state, which greatly influences the erroneous write-in characteristics.
In order to reduce the Vpgm stress, several channel voltage control methods have been proposed. The conventional methods have been proposed from the perspective of how to increase the efficiency in boosting the channel voltage. However, the conventional methods are approaching a limitation, and improvement in boost efficiency is becoming difficult. The present invention proposes to increase the channel charge Qch prior to boosting so as to improve erroneous write-in characteristics by decreasing the number of electrons remaining in the channel.
In other words, the present invention provides a nonvolatile semiconductor memory which, in the case of performing sequential write-in, applies a dummy pulse to a control gate line before applying pulses of intermediate voltage Vpass and write-in voltage Vpgm so as to reduce the number of electrons existing in the channel and the diffusion layer region in a NAND cell unit, thereby improving channel voltage. Furthermore, a highly versatile nonvolatile semiconductor memory, which discharges excessively-introduced electrons from the NAND cell unit, is used in combination with the channel voltage boosting method.